Santa Clara

RVfpga: Understanding Computer Architecture In-person Workshop-Dec. 15th

Thu, Dec 15, 2022
09:00am - 05:00pm
Thu, Dec 15, 2022
09:00am - 05:00pm
Santa Clara
UCSC Silicon Valley: University of California, Extension Training Center, Room 2110, 3175 Bowers Avenue, Santa Clara, California
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Free
Free

Date

Thu, Dec 15, 2022
09:00am - 05:00pm
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Location

UCSC Silicon Valley: University of California, Extension Training Center, Room 2110, 3175 Bowers Avenue, Santa Clara, California
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Price

Free
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Description

RVfpga: Understanding Computer Architecture In-person Workshop-Dec. 15th is happening on Thursday, December 15, 2022 at 09:00AM PST at UCSC Silicon Valley: University of California, Extension Training Center and It's Free

QUESTIONS? e-mail: IUP@imgtec.com

Travel information

*Location: UCSC Extension Center is at the junction of US Route 101 & The Great Americas Parkway.About 20 minutes drive from the San Jose Conference Center, where the RISC-V Summit is being held.

The RVfpga Workshop is a separate event and attendance is free.

DEMAND IS HIGH, so we have funded both the co-authors of RVfpga to be Trainers!



RVfpga (RISC-V fpga) Understanding Computer Architecture - A Hands-On, In-Person, One-Day-Workshop

Bring RISC-V to your course in computer architecture using RVfpga

This workshop shows how to use RISC-V to teach computer architecture and the design of systems on chip (SoCs). Let us empower you to teach next generation computer science, electrical and computer engineering students with hands-on real-world expertise in computer architecture and the RISC-V instruction set architecture.

What is the RVfpga workshop about?

RISC-V is a rapidly growing world-wide movement. It is open source and provides extensions, making it easier to target to various platforms. This RVfpga workshop presents a commercial RISC-V system targeted to an FPGA, discusses the theory, architecture, and course structure, and shows how to use the hands-on labs that are provided as part of the complete RISC-V FPGA (RVfpga) Course. The course explores the fundamentals of computer architecture using Western Digital’s open-source, commercial SweRV EH1 RISC-V core targeted to a Xilinx Artix 7 FPGA on Digilent’s Nexys A7 development board. Everyone will get hands-on experience with this FPGA platform and the software tools, enabling a fast start when you return to your university.

What will you learn?

The workshop shows how to quickly get the RISC-V FPGA system and RISC-V tools up and running. Then, we describe all of the RVfpga labs and show how to use and work through a selection of the labs hands-on. We also discuss how to integrate RVfpga into your curriculum.

Specific topics include:

* Installing tools (which can be done before the workshop)

* Targeting the SweRV EH1 RISC-V core to an FPGA

* Analyzing and modifying the RISC-V-core and memory hierarchy

Workshop Schedule:9AM to 5PM

Draft Schedule:

- Welcome, Introductions and Set-up

- Introduction to the teaching materials and workshop

>>Break

- Instruction and Hands-On Labs

Supporting Organisations:

- Overview of the Imagination University Programme, by Robert Owen (Imagination)

- The Digi-Key Academic Program, by YC Wang

>> Lunch Break and Networking

- Instruction and Hands-On Labs

- Feedback Forms

>>Break

- How to fit RVfpga into your curriculum, Your next steps, Q&A

*The schedule for the day is subject to change. So that you can plan your travel, we will not start earlier than 9AM and our finish will be 5PM latest.

Materials:

All delegates will be given access to the lecture slides and course notes, programming exercises and solutions as well as example exam questions and answers. In addition, Digilent Nexys 4 DDR or A7 boards will be provided for delegates to have hands-on experience. However, they are not give-aways -please return them before you leave the workshop.

Please bring your own laptop.

Catering:

Please feel free to arrive before 9am and grab yourself some breakfasts. Light lunches will be provided in the lunch break. Coffee, tea and water will be available all day.

WiFi:

Free standard simple guest subscribe login will be provided.

Your Trainers:

Sarah L. Harris is Professor of Electrical and Computer Engineering at the University of Nevada, Las Vegas. She earned her M.S. and Ph.D. at Stanford University. Before joining UNLV in 2014, she was a faculty member at Harvey Mudd College from 2004-2014. She has also worked at Hewlett Packard, Nvidia, and the Technical University of Darmstadt and has collaborated with other companies including Southwest Research Institute, Intel, and Imagination Technologies. She is the co-author of three popular textbooks: Digital Design and Computer Architecture, 2nd Edition (2007), ARM Edition (2015), and RISC-V Edition (2021). Dr. Harris is also currently leading or co-leading two NSF-funded grants on Smart Cities and on integrating family support in STEM education. Her research interests include computer architecture and applications of embedded systems and machine learning to biomedical engineering and robotics.

Daniel A. Chaver Martínezobtained a Physics Degree from University of Santiago de Compostela (USC) in 1998 and an Electronic Engineering Degree from University Complutense of Madrid (UCM) in 2000. He developed his PhD from 2000 to 2006 at UCM. He has tought many different courses related to Computer Architecture since 2000. His current research interests include: Architectural Techniques for the Cache and for Non-volatile Memories and OS Scheduling for Asymmetric MultiProcessors. Since 2015, he has been collaborating with Imagination Technologies in the developement of some of their processors and teaching materials.

For more information about the Imagination University Programme and RVfpgaCLICK HERE.

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